[SOLVED] Getting jlink debug SAME70 with a Bootloader

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  • [SOLVED] Getting jlink debug SAME70 with a Bootloader

    Hello,I am using a jlink(sam-ice) to debug a SAME70.I want to use jlink to debug it,but I have a bootloader in it.When I click debug in Keil,jlink jump to 0x40000 where is my bootloader begins instead of where is my application's address.According to mannal(UM08001),it seems I can debug from and address by creating a "jlink script".But I didn't found
    any example about CORTEX-M core.Can you give me an example (SAME70 if possible) of CORTEX-M .Is there any tutorial about how to write the "ResetTaget" function in jlink script?


    Best regards :)
  • Hi,


    do I understand you correctly that you do not just want to execute the bootloader and then set a break point in the main program, but
    instead want to jump directly to the start address of your main application after a reset?

    You need to pass a J-Link Script file witch contains a ResetTarget() function in order to override the default behavior.

    C Source Code

    1. /*********************************************************************
    2. *
    3. * ResetTarget
    4. */
    5. void ResetTarget(void) {
    6. //
    7. // Insert desired reset behavior here
    8. //
    9. }


    Examples scripts are shipped with the J-Link software package. They be found in _JLinkInstallDir_\Samples\JLink\Scripts
    e.g. Renesas_RZG1M_ConnectCore0.JLinkScript

    C Source Code

    1. /*********************************************************************
    2. *
    3. * ResetTarget
    4. */
    5. void ResetTarget(void) {
    6. int v;
    7. int Speed;
    8. int Ctrl;
    9. Report("******************************************************");
    10. Report("J-Link script: ResetTarget()");
    11. Report("******************************************************");
    12. Speed = JTAG_Speed;
    13. JTAG_Speed = 100;
    14. JTAG_WriteClocks(1);
    15. //
    16. // Select APB-AP and prepare control register
    17. //
    18. JLINK_CORESIGHT_WriteDP(2, (1 << 24) | (0 << 4)); // Select AP[1], bank 0
    19. Ctrl = 0
    20. | (2 << 0) // AP-access size. Fixed to 2: 32-bit
    21. | (1 << 4) // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
    22. | (1 << 31) // Enable software access to the Debug APB bus.
    23. ;
    24. JLINK_CORESIGHT_WriteAP(0, Ctrl);
    25. //
    26. // Perform some other init steps which are required to get full control of the debug logic
    27. //
    28. JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0xFB0);
    29. JLINK_CORESIGHT_WriteAP(3, 0xC5ACCE55);
    30. JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x310);
    31. JLINK_CORESIGHT_WriteAP(3, 1);
    32. JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x314);
    33. JLINK_CORESIGHT_ReadAP(3);
    34. v = JLINK_CORESIGHT_ReadDP(3);
    35. //
    36. // Read & modify DSCR in order to enable debug halt mode
    37. //
    38. JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x88);
    39. JLINK_CORESIGHT_ReadAP(3);
    40. v = JLINK_CORESIGHT_ReadDP(3);
    41. v |= (1 << 14);
    42. JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x88); // Enable debug halt mode by writing the DSCR
    43. JLINK_CORESIGHT_WriteAP(3, v);
    44. //
    45. // Halt CPU by writing the halt request bit in the DRCR
    46. //
    47. JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x90);
    48. JLINK_CORESIGHT_WriteAP(3, 1);
    49. JTAG_WriteClocks(1);
    50. JTAG_Speed = Speed;
    51. }
    Display All


    Currently, there are no function to read / write CPU registers directly. You need to use the JLINK_CORESIGHT functions in order to change the value of the PC.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Yes,I've read this example but still don't know how to write the reset function because all of your examples are about cortex-A but no cortex-m core.The reset behavior has a lots of differences among them and I have no idea how to write the reset function so I am here to find out is there any further information about it.







    Best regards
  • Yes,I've read this example but still don't know how to write the reset function because all of your examples are about cortex-A but no cortex-m core.The reset behavior has a lots of differences among them and I have no idea how to write the reset function so I am here to find out is there any further information about it.


    Best regards
  • Hi,

    I prepared an example script file for STM32F4 devices:

    C Source Code

    1. /*********************************************************************
    2. *
    3. * Peripherals
    4. */
    5. // #define AIRCR_ADDR 0xE000ED0C
    6. // #define DHCSR_ADDR 0xE000EDF0
    7. // #define DEMCR_ADDR 0xE000EDFC
    8. /*********************************************************************
    9. *
    10. * AHBAP registers
    11. */
    12. // #define AHBAP_REG_CTRL 0
    13. // #define AHBAP_REG_ADDR 1
    14. // #define AHBAP_REG_DATA 3
    15. /*********************************************************************
    16. *
    17. * DP / AP registers
    18. */
    19. // #define DP_REG_SELECT 2
    20. /*********************************************************************
    21. *
    22. * ResetTarget()
    23. * Reset and wait until CPU is halted.
    24. */
    25. void ResetTarget(void) {
    26. int AIRCR_ADDR ;
    27. int DHCSR_ADDR ;
    28. int DEMCR_ADDR ;
    29. int AHBAP_REG_CTRL ;
    30. int AHBAP_REG_ADDR ;
    31. int AHBAP_REG_DATA ;
    32. int DP_REG_SELECT ;
    33. AIRCR_ADDR = 0xE000ED0C;
    34. DHCSR_ADDR = 0xE000EDF0;
    35. DEMCR_ADDR = 0xE000EDFC;
    36. AHBAP_REG_CTRL = 0;
    37. AHBAP_REG_ADDR = 1;
    38. AHBAP_REG_DATA = 3;
    39. DP_REG_SELECT = 2;
    40. int Ctrl;
    41. int demcr;
    42. int v;
    43. int Tries;
    44. int Done;
    45. if (MAIN_ActiveTIF == JLINK_TIF_JTAG) {
    46. JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
    47. } else {
    48. JLINK_CORESIGHT_Configure(""); // For SWD, no special setup is needed, just output the switching sequence
    49. }
    50. //
    51. // Power-up complete DAP
    52. //
    53. Ctrl = 0
    54. | (1 << 30) // System power-up
    55. | (1 << 28) // Debug popwer-up
    56. | (1 << 5) // Clear STICKYERR
    57. ;
    58. JLINK_CORESIGHT_WriteDP(1, Ctrl);
    59. //
    60. // Select AHB-AP and configure it
    61. //
    62. JLINK_CORESIGHT_WriteDP(DP_REG_SELECT, (0 << 4) | (0 << 24)); // Select AP[0] (AHB-AP) bank 0
    63. JLINK_CORESIGHT_WriteAP(AHBAP_REG_CTRL, (1 << 4) | (1 << 24) | (1 << 25) | (1 << 29) | (2 << 0)); // Auto-increment, Private access, HMASTER = DEBUG, Access size: word
    64. JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
    65. v = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
    66. v &= 0x3F; // Mask out "debug" bits
    67. v |= 0xA05F0000; // Debug key to make a write to the DHCSR a valid one
    68. v |= 0x00000002; // Halt the core
    69. v |= 0x00000001; // Enable debug functionalities of the core
    70. JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
    71. JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, v);
    72. //
    73. // Set VC_CORERESET
    74. //
    75. JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
    76. demcr = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
    77. JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
    78. JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, demcr | 0x00000001);
    79. //
    80. // SYSRESETREQ
    81. //
    82. JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, AIRCR_ADDR);
    83. JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0x05FA0004);
    84. //
    85. // Wait until CPU is halted
    86. //
    87. Tries = 0;
    88. Done = 0;
    89. do {
    90. JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
    91. v = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
    92. //
    93. // Check if CPU is halted. If so, we are done
    94. //
    95. if (Tries >= 5) {
    96. MessageBox("STM32 (connect): Timeout while waiting for CPU to halt after reset. Manually halting CPU.");
    97. Done = 1;
    98. }
    99. if (v & 0x00020000) { // 1 << 17
    100. Done = 1;
    101. }
    102. Tries = Tries + 1;
    103. SYS_Sleep(100);
    104. } while(Done == 0);
    105. }
    Display All


    Please note that you may need to adjust this example in order to use it with SAME70.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Thanks for the script!It seems work since the chip reset with script acts like it uses a default reset define by the DLL.
    But when I use "CORESIGHT_CoreBaseAddr" variables to control where the program starts,it didn't work.What's the problem in it?
  • According to the UM08001 the "CORESIGHT_CoreBaseAddr" should be R/W but when I try to print it by function "Report1",it shows "Error while parsing script file .... Variable is write-only".Is it write-only or I shouldn't print it by "Report1"?
  • Hi,


    I could reproduce this issue.
    I will check whether this is an documentation or implementation issue.


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi,


    CORESIGHT_CoreBaseAdd is not the variable you are looking for:
    Sets base address of core debug component for
    CoreSight compliant devices. Setting this vari-
    able disables the J-Link auto-detection of the
    core debug component base address. Used on
    devices where auto-detection of the core debug
    component base address is not possible due to
    incorrect CoreSight information.


    Currently, we can not provide an example for setting the PC by using CoreSight.
    Convenience functions like SetPC() are planned for a future release of the J-Link software & documentation pack, but without a fixed release yet.
    Until then, you need either to consult the CoreSight Components manual and the reference manual of the AtSAME70 or stick with a simpler solution, e.g. removing the bootloader temporary and directly start with the application.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.