[SOLVED] STM32F746 Failed to execute RAMCode for RAM check! after upgrade to jlink 5.02e

abstractsig · Oct 2nd 2015, 5:13am

Hi,

I have a STMF746 board that i was connecting to, via Jtag, using jlink/jlink GDB 5.02b.

I have just upgraded to 5.02e and now cannot programme or debug the STM32F746. Also I tried to go back to using 5.02b but this will not work for me anymore either.

When I upgraded to 5.02e the jlink firmware updated to:

Firmware: J-Link V9 compiled Sep 18 2015 19:53:12
Hardware: V9.20

I get this error in the log:

ERROR: Failed to prepare for programming.
Failed to execute RAMCode for RAM check!

Can anyone explain what "RAMCode" is? Is this a new jlink feature?

Thanks

Gregor Bruce

This is the GDB server log

Listening on TCP/IP port 2331
Connecting to target...
J-Link found 2 JTAG devices, Total IRLen = 9
JTAG ID: 0x5BA00477 (Cortex-M4)
Connected to target
Waiting for GDB connection...Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x08000200 (Data = 0x4A32B5F8)
Resetting target
Downloading 1560 bytes @ address 0x08000000
Downloading 4096 bytes @ address 0x08008000
Downloading 4096 bytes @ address 0x08009000
Downloading 4096 bytes @ address 0x0800A000

....
....
....

Downloading 4096 bytes @ address 0x08043000
Downloading 4096 bytes @ address 0x08044000
Downloading 823 bytes @ address 0x08045000
Downloading 8 bytes @ address 0x08045338
Downloading 3968 bytes @ address 0x08045340
Downloading 456 bytes @ address 0x20000000
ERROR: Failed to prepare for programming.
Failed to execute RAMCode for RAM check!
Read 4 bytes @ address 0x08000200 (Data = 0x4A32B5F8)
Read 4 bytes @ address 0x08000200 (Data = 0x4A32B5F8)

SEGGER - Roman · Oct 5th 2015, 11:03am

Hi Gregor,

We did a quick check with the J-Link Commander V5.02f and a STM32F756 eval board and programming works as expected.

The RAMCode is downloaded temporarily into the target's RAM and is used to handle programming.

Can you please give us a J-Link log file of a session in which this behavior pops up ( Please in a zip container)? The J-Link log file can be enabled in the J-Link Control Panel -> Settings tab (green J-Link icon in the windows task bar during a connection to the J-Link is open).

Best regards,

Roman

abstractsig · Oct 5th 2015, 9:10pm

Log file attached.

Note on hardware, I am using a STM32F746 discovery board modified to connect jlink to the CPU's JTAG interface bypassing the on-board STLINK. I had successfully loaded and executed the binary used in the attached log prior to upgrading from 5.02b.

I get almost the same output as your image above when i run jlink from a command console:

$ jlink -device STM32F746NG
SEGGER J-Link Commander V5.02f ('?' for help)
Compiled Oct 2 2015 20:52:00
Info: Device "STM32F746NG" selected.
DLL version V5.02f, compiled Oct 2 2015 20:51:34
Firmware: J-Link V9 compiled Sep 18 2015 19:53:12
Hardware: V9.20
S/N: 59200607
Feature(s): GDB
Emulator has Trace capability
VTarget = 3.285V
Info: TotalIRLen = 9, IRPrint = 0x0011
Info: TotalIRLen = 9, IRPrint = 0x0011
Info: Found Cortex-M7 r0p1, Little endian. <==== difference, core is r0p1
Info: FPUnit: 8 code (BP) slots and 0 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FD000
Info: ROMTbl 0 [0]: 00001000, CID: B105100D, PID: 000BB4C8 ROM Table
Info: ROMTbl 1 @ E00FE000
Info: ROMTbl 1 [0]: 00001000, CID: B105100D, PID: 000BB4C7 ROM Table
Info: ROMTbl 2 @ E00FF000
Info: ROMTbl 2 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 2 [1]: FFF02000, CID: B105E00D, PID: 000BB002 DWT
Info: ROMTbl 2 [2]: FFF03000, CID: B105E00D, PID: 000BB00E FPB
Info: ROMTbl 2 [3]: FFF01000, CID: B105E00D, PID: 000BB001 ITM
Info: ROMTbl 1 [1]: FFF43000, CID: B105900D, PID: 000BB975 ETM-M7
Info: ROMTbl 0 [1]: FFF43000, CID: B105900D, PID: 000BB9A9 TPIU-M7
Cache: Separate I- and D-cache.
Info: I-Cache L1: 4 KB, 64 Sets, 32 Bytes/Line, 2-Way
Info: D-Cache L1: 4 KB, 32 Sets, 32 Bytes/Line, 4-Way
Found 2 JTAG devices, Total IRLen = 9:
#0 Id: 0x5BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
#1 Id: 0x06449041, IRLen: 05, Unknown device
Cortex-M7 identified.
Target interface speed: 100 kHz

Thanks
Gregor Bruce

lix · Oct 16th 2015, 6:30pm

Hi,

I have the same problem as Bruce, i.e.: I use the same STM32F746G-Disco board modified to connect the J-Link over SWD (I removed the local ST-Link V2) and I get the same message when e.g. I try to erase the controller:

imac:~ lix$ /Applications/SEGGER/JLink/JLinkExe
SEGGER J-Link Commander V5.02f ('?' for help)
Compiled Oct 2 2015 20:55:08
DLL version V5.02f, compiled Oct 2 2015 20:55:03
Firmware: J-Link V9 compiled Sep 18 2015 19:53:12
Hardware: V9.30
S/N: 59304371
Feature(s): GDB
Emulator has Trace capability
VTarget = 3.282V
Info: Found SWD-DP with ID 0x5BA02477
Info: Found Cortex-M7 r0p1, Little endian.
Info: FPUnit: 8 code (BP) slots and 0 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FD000
Info: ROMTbl 0 [0]: 00001000, CID: B105100D, PID: 000BB4C8 ROM Table
Info: ROMTbl 1 @ E00FE000
Info: ROMTbl 1 [0]: 00001000, CID: B105100D, PID: 000BB4C7 ROM Table
Info: ROMTbl 2 @ E00FF000
Info: ROMTbl 2 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 2 [1]: FFF02000, CID: B105E00D, PID: 000BB002 DWT
Info: ROMTbl 2 [2]: FFF03000, CID: B105E00D, PID: 000BB00E FPB
Info: ROMTbl 2 [3]: FFF01000, CID: B105E00D, PID: 000BB001 ITM
Info: ROMTbl 1 [1]: FFF43000, CID: B105900D, PID: 000BB975 ETM-M7
Info: ROMTbl 0 [1]: FFF43000, CID: B105900D, PID: 000BB9A9 TPIU-M7
Cache: No cache
Found 1 JTAG device, Total IRLen = 4:
Cortex-M7 identified.
Target interface speed: 100 kHz
J-Link>device STM32f746ng
Info: Device "STM32F746NG" selected.
Reconnecting to target...
Info: Found SWD-DP with ID 0x5BA02477
Info: Found SWD-DP with ID 0x5BA02477
Info: Found Cortex-M7 r0p1, Little endian.
Info: FPUnit: 8 code (BP) slots and 0 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FD000
Info: ROMTbl 0 [0]: 00001000, CID: B105100D, PID: 000BB4C8 ROM Table
Info: ROMTbl 1 @ E00FE000
Info: ROMTbl 1 [0]: 00001000, CID: B105100D, PID: 000BB4C7 ROM Table
Info: ROMTbl 2 @ E00FF000
Info: ROMTbl 2 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 2 [1]: FFF02000, CID: B105E00D, PID: 000BB002 DWT
Info: ROMTbl 2 [2]: FFF03000, CID: B105E00D, PID: 000BB00E FPB
Info: ROMTbl 2 [3]: FFF01000, CID: B105E00D, PID: 000BB001 ITM
Info: ROMTbl 1 [1]: FFF43000, CID: B105900D, PID: 000BB975 ETM-M7
Info: ROMTbl 0 [1]: FFF43000, CID: B105900D, PID: 000BB9A9 TPIU-M7
Cache: Separate I- and D-cache.
Info: I-Cache L1: 0 KB, 1 Sets, 16 Bytes/Line, 1-Way
Info: D-Cache L1: 4 KB, 32 Sets, 32 Bytes/Line, 4-Way
J-Link>erase
Erasing device (STM32F746NG)...

****** Error: Failed to prepare for programming.
Failed to execute RAMCode for RAM check!
ERROR: Erase returned with error code -1.
J-Link>

If I am using a standalone ST-Link V2 (under Windows) I can erase and program the chip. Any ideas what can it be?

Lix

lix · Oct 20th 2015, 12:50am

The issue was that the WWDG-SW option bit was unset, so that the controller had the watchdog enabled when getting out of reset. After about 10 ms the watchdog would reset the controller, therefore no operation was possible. After setting this bit using the ST-LINK, everything went back to normal. Are there any means to manipulate the option bits with the J-Link (e.g. using the command line)?

Lix

SEGGER - Roman · Oct 21st 2015, 9:28am

Hi Lix,

Thanks for pointing that out. We plan to have a new Version of the J-Link software available at the end of this week.
Of course the option bytes can be set with the JLink Commander. Please refer to chapter 3.4.2 of the ST manual for further information
how to program the option bytes.

- Roman

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