Hi,
I have a similar issue as in "Thread 2538" but I didn't find the solution there.
When trying to connect (in IAR IDE, "Debug without downloading") I get following output:
Thu Sep 03, 2015 08:44:08: JLINK command: ProjectFile = H:\<...blabla....>\settings\HelloMock_Release.jlink, return = 0
Thu Sep 03, 2015 08:44:08: Device "UNSPECIFIED" selected.
Thu Sep 03, 2015 08:44:08: DLL version: V5.0f, compiled Jun 30 2015 18:58:49
Thu Sep 03, 2015 08:44:08: Firmware: J-Link ARM V8 compiled Nov 28 2014 13:44:46
Thu Sep 03, 2015 08:44:08: Selecting SWD as current target interface.
Thu Sep 03, 2015 08:44:08: JTAG speed is initially set to: 32 kHz
Thu Sep 03, 2015 08:44:08: Found SWD-DP with ID 0x0BB11477
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Hardware reset with strategy 0 was performed
Thu Sep 03, 2015 08:44:09: Initial reset was performed
Thu Sep 03, 2015 08:44:09: Found SWD-DP with ID 0x0BB11477
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Found SWD-DP with ID 0x0BB11477
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
I try to connect to an FPGA running my own customized ARM-Cortex-M0 (means I'm not using any specific STM32 platform or whatever).
The M0 is configured to use SWD (no JTAG), there is only one power domain for the whole chip, so for sure the debug power domain is powered up. Debug is enabled on the M0 as well.
The M0 is running before I try to connect, it is executing some code from internal ROM (there is no flash on the FPGA).
Could you please point me into a direction to further investigate? At the moment I'm stuck with this Jlink warning...
Thank you very much,
Daniel
I have a similar issue as in "Thread 2538" but I didn't find the solution there.
When trying to connect (in IAR IDE, "Debug without downloading") I get following output:
Thu Sep 03, 2015 08:44:08: JLINK command: ProjectFile = H:\<...blabla....>\settings\HelloMock_Release.jlink, return = 0
Thu Sep 03, 2015 08:44:08: Device "UNSPECIFIED" selected.
Thu Sep 03, 2015 08:44:08: DLL version: V5.0f, compiled Jun 30 2015 18:58:49
Thu Sep 03, 2015 08:44:08: Firmware: J-Link ARM V8 compiled Nov 28 2014 13:44:46
Thu Sep 03, 2015 08:44:08: Selecting SWD as current target interface.
Thu Sep 03, 2015 08:44:08: JTAG speed is initially set to: 32 kHz
Thu Sep 03, 2015 08:44:08: Found SWD-DP with ID 0x0BB11477
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Hardware reset with strategy 0 was performed
Thu Sep 03, 2015 08:44:09: Initial reset was performed
Thu Sep 03, 2015 08:44:09: Found SWD-DP with ID 0x0BB11477
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Found SWD-DP with ID 0x0BB11477
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
Thu Sep 03, 2015 08:44:09: Warning: Could not power-up debug power domain.
I try to connect to an FPGA running my own customized ARM-Cortex-M0 (means I'm not using any specific STM32 platform or whatever).
The M0 is configured to use SWD (no JTAG), there is only one power domain for the whole chip, so for sure the debug power domain is powered up. Debug is enabled on the M0 as well.
The M0 is running before I try to connect, it is executing some code from internal ROM (there is no flash on the FPGA).
Could you please point me into a direction to further investigate? At the moment I'm stuck with this Jlink warning...
Thank you very much,
Daniel