Cannot connect. "WARNING: Could not power-up debug power domain."

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  • Cannot connect. "WARNING: Could not power-up debug power domain."

    Hi,

    I am a new owner and user of a J-LINK EDU. When I try to connect it to my Cortex M0 board through the SWD port I get the following message. Can you tell me what the WARNING means and how to fix it.

    Thanks and Regards,
    Nick

    SEGGER J-Link Commander V5.00k ('?' for help)
    Compiled Jul 31 2015 15:49:17
    DLL version V5.00k, compiled Jul 31 2015 15:48:52
    Firmware: J-Link V9 compiled Jun 23 2015 10:00:59
    Hardware: V9.30
    S/N: 269305033
    OEM: SEGGER-EDU
    Feature(s): FlashBP, GDB
    Emulator has Trace capability
    VTarget = 3.293V
    Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
    Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
    No devices found on JTAG chain. Trying to find device on SWD.
    Info: Found SWD-DP with ID 0x0BB11477

    **************************
    WARNING: Could not power-up debug power domain.
    **************************


    **************************
    WARNING: Could not power-up debug power domain.
    **************************


    **************************
    WARNING: Could not power-up debug power domain.
    **************************


    ****** Error: Cortex-A/R check: Communication error when trying to read IDR of A
    P[0].
    Cortex-A/R (connect): Communication error when trying to read IDR of AP[0].
    Info: Found SWD-DP with ID 0x0BB11477

    **************************
    WARNING: Could not power-up debug power domain.
    **************************


    **************************
    WARNING: Could not power-up debug power domain.
    **************************


    **************************
    WARNING: Could not power-up debug power domain.
    **************************


    ****** Error: Cortex-A/R check: Communication error when trying to read IDR of A
    P[0].
    Cortex-A/R (connect): Communication error when trying to read IDR of AP[0].
    No device found on SWD.
    Trying to find device on FINE interface.
    No device found on FINE interface.
    Did not find any core.
    Failed to identify target. Trying again with slow (4 kHz) speed.
    No devices found on JTAG chain. Trying to find device on SWD.
    No device found on SWD.
    Trying to find device on FINE interface.
    No device found on FINE interface.
    Did not find any core.
    No device found at all. Selecting JTAG as default target interface.
    J-Link>
  • I have tried several times to connect to J-Link with most attempts failing with the above error message. However, I did get it once to connect. See the J-Link log below. I would be thankful for any comments.

    Regards,
    Nick

    SEGGER J-Link Commander V5.00k ('?' for help)
    Compiled Jul 31 2015 15:49:17
    DLL version V5.00k, compiled Jul 31 2015 15:48:52
    Firmware: J-Link V9 compiled Jun 23 2015 10:00:59
    Hardware: V9.30
    S/N: 269305033
    OEM: SEGGER-EDU
    Feature(s): FlashBP, GDB
    Emulator has Trace capability
    VTarget = 3.293V
    Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
    Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
    No devices found on JTAG chain. Trying to find device on SWD.
    Info: Found SWD-DP with ID 0x0BB11477
    Info: Found Cortex-M0 r0p0, Little endian.
    Info: FPUnit: 4 code (BP) slots and 0 literal slots
    Info: CoreSight components:
    Info: ROMTbl 0 @ E00FF000
    Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB008 SCS
    Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 000BB00A DWT
    Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 000BB00B FPB
    Cortex-M0 identified.
    Target interface speed: 100 kHz
    J-Link>
  • Hi Nick,

    What target device are you using?
    Are you using custom hardware or an evaluation board? In the latter case, what's the name of the board?

    - Erik
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi Nick,
    Cortex M0
    can you specify which device you are trying to connect to?

    Could you try to call J-Link Commander with a device specified ? e.g. "JLink.exe -Device STM32F103ZE"

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • SEGGER - Niklas wrote:

    Hi Nick,
    Cortex M0
    can you specify which device you are trying to connect to?

    Could you try to call J-Link Commander with a device specified ? e.g. "JLink.exe -Device STM32F103ZE"

    Best regards,
    Niklas
    Hi Niklas,

    I do not know the device name. It is an embedded M0 in a sensor chip that I talk to (in functional mode) with either SPI or I2C. The register set is very simple as is the control of loading the M0 code in flash and running it. I have successfully done this. There is an unlock sequence that I must first use and an enable bit for the DAP interface. Both seem to work.

    It seems that, in order to get a successful connection with JLink, I must first run a program to unlock and enable DAP. However, I seem to have to do this several times (at least twice) before I get a connect. The first time fails with the above warning about the debug power domain. Is this really a power issue? Could it be that running the program at least once turns on this power domain?

    Thanks and Regards,
    Nick
  • Cortex M0 r0p0 is just the architecture but not the device name. We need the device manufacturer + device name (e.g. ST STM32F103ZE, Atmel ATSAM3S1A, etc....).

    - Erik
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • SEGGER - Erik wrote:

    Cortex M0 r0p0 is just the architecture but not the device name. We need the device manufacturer + device name (e.g. ST STM32F103ZE, Atmel ATSAM3S1A, etc....).

    - Erik
    Hi Erik,

    I do not know the device name because it is an embedded device in a sensor chip. All I know is that it is an M0. It is not a standalone micro chip like the kind that you would buy from ST or Atmel. Will this be an issue?

    Nick
  • Hi Nick,

    the major part of devices will work without J-Link knowing the device name (= J-Link using auto detection), however a decent amount of devices does not and need special handling.
    J-Link can only execute a special handling if it gets the device name passed.
    In your case, the J-Link seems the read an invalid AP ID while trying to figure out if it is a Cortex A/R device.
    It seems that, in order to get a successful connection with JLink, I
    must first run a program to unlock and enable DAP. However, I seem to
    have to do this several times (at least twice) before I get a connect.
    The first time fails with the above warning about the debug power
    domain. Is this really a power issue? Could it be that running the
    program at least once turns on this power domain?

    I can ask if this behavior seems familiar to sb., but since there are a lot of devices, it would really help to identify or narrow down this device.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • SEGGER - Niklas wrote:

    Hi Nick,

    the major part of devices will work without J-Link knowing the device name (= J-Link using auto detection), however a decent amount of devices does not and need special handling.
    J-Link can only execute a special handling if it gets the device name passed.
    In your case, the J-Link seems the read an invalid AP ID while trying to figure out if it is a Cortex A/R device.
    It seems that, in order to get a successful connection with JLink, I
    must first run a program to unlock and enable DAP. However, I seem to
    have to do this several times (at least twice) before I get a connect.
    The first time fails with the above warning about the debug power
    domain. Is this really a power issue? Could it be that running the
    program at least once turns on this power domain?

    I can ask if this behavior seems familiar to sb., but since there are a lot of devices, it would really help to identify or narrow down this device.

    Best regards,
    Niklas
    Hi Niklas,

    Unfortunately it is a device that Segger does not now support. But it is a device whose architecture (M0) Segger does support. With this device the J-Link can read and write the SRAM just fine. However, the FLASH, for which J-Link reads work, has problems with writes. This is most likely due to the type of FLASH the device uses, in particular, the erasing and writing rules that must be followed. Is there a way to modify the J-Link FLASH writing routines to support this particular flash's writing rules? Say in a script?

    What I will work on first is getting the J-Link debugger to work with code in SRAM. This I am hopeful will work. Then, if the J-Link flash routines are scriptable, I will try the flash.

    Thanks and regards,
    Nick

    The post was edited 1 time, last by photon ().

  • Hi Nick,
    Is there a way to modify the J-Link FLASH writing routines to support this particular flash's writing rules? Say in a script?
    there are a few options :

    1) Open flash loader
    We plan to implement a new J-Link DLL extension called open flash loader which will allow customers to write / use their own flash algorithms with J-Link.
    We plan to release Open flash loader later this year. If you are interested in, I can add you to the J-Link software and update notification system,
    so that you get informed automatically, once new versions of the J-Link software are available.

    2) Manual Flash algorithm

    You have to write a small application (flash loader) which you have to download into the RAM (using the loadfile command),
    afterwards the data have to be written into a defined RAM area (which is used by the data application as data source).
    Now set the PC to the start of the flash loader, set a breakpoint at the last instruction and run the code.
    Repeat this, until all data has been programmed.

    3) J-Flash + custom RamCode

    Furthermore, we offer a custom RAMCode SDK (free of charge) which allows customers to create a custom RAMCode.
    This custom RAMCode can be used within J-Flash to program / erase custom areas . For further information regarding J-Flash, please refer to the J-Flash manual:
    segger.com/admin/uploads/productDocs/UM08003_JFlash.pdf

    In order to use J-Flash, you will need to acquire either a
    J-Link Base + J-Flash License or a
    J-Link PLUS or higher.


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • SEGGER - Niklas wrote:

    there are a few options :

    1) Open flash loader
    We plan to implement a new J-Link DLL extension called open flash loader which will allow customers to write / use their own flash algorithms with J-Link.
    We plan to release Open flash loader later this year. If you are interested in, I can add you to the J-Link software and update notification system,
    so that you get informed automatically, once new versions of the J-Link software are available.

    2) Manual Flash algorithm

    You have to write a small application (flash loader) which you have to download into the RAM (using the loadfile command),
    afterwards the data have to be written into a defined RAM area (which is used by the data application as data source).
    Now set the PC to the start of the flash loader, set a breakpoint at the last instruction and run the code.
    Repeat this, until all data has been programmed.


    Hi Niklas,

    I like the upcoming Open flash loader. Yes, please add me to the J-Link software and update notification system. Will the user be able to set breakpoints using this Open flash loader?

    Thanks for the info about the Manual flash loader. Yes, I see how that would work. The downside appears to me that you will not be able to set breakpoints in the flash. Is this correct?

    Thanks and Regards,
    Nick
  • Hi Nick,
    Thanks for the info about the Manual flash loader. Yes, I see how that
    would work. The downside appears to me that you will not be able to set
    breakpoints in the flash. Is this correct?
    correct.
    I have added you the J-Link (Beta) update notification list.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.