AM335x ETB

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  • How do you enable the ETB on the AM3352? My J-Link sees the ARM core, but not the ETB.

    Source Code

    1. C:\Program Files\SEGGER\JLink_V496l>jlink -device am3359
    2. SEGGER J-Link Commander V4.96l ('?' for help)
    3. Compiled Feb 25 2015 10:24:24
    4. Info: Device "AM3359" selected.
    5. DLL version V4.96l, compiled Feb 25 2015 10:24:11
    6. Firmware: J-Link V9 compiled Feb 20 2015 09:20:19
    7. Hardware: V9.30
    8. S/N: 59302970
    9. Feature(s): GDB
    10. VTarget = 3.306V
    11. Info: TotalIRLen = 6, IRPrint = 0x01
    12. Info: TotalIRLen = 10, IRPrint = 0x0011
    13. Info: CoreSight AP[0]: 0x04770001, AHB-AP
    14. Info: CoreSight AP[1]: 0x04770002, APB-AP
    15. Info: CoreSight AP[2]: 0x04760000, JTAG-AP
    16. Info: Found Cortex-A8 r3p2
    17. Info: 6 code breakpoints, 2 data breakpoints
    18. Info: Debug architecture ARMv7.0
    19. Info: Data endian: little
    20. Info: Main ID register: 0x413FC082
    21. Info: I-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
    22. Info: D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
    23. Info: Unified-Cache L2: 256 KB, 512 Sets, 64 Bytes/Line, 8-Way
    24. Info: System control register:
    25. Info: Instruction endian: little
    26. Info: Level-1 instruction cache enabled
    27. Info: Level-1 data cache disabled
    28. Info: MMU disabled
    29. Info: Branch prediction enabled
    30. Found 2 JTAG devices, Total IRLen = 10:
    31. #0 Id: 0x3BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
    32. #1 Id: 0x0B94402F, IRLen: 06, IRPrint: 0x1, TI ICEPick
    33. Cortex-A8 identified.
    34. Target interface speed: 100 kHz
    35. J-Link>etb
    36. ETB is not present.
    37. J-Link>
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  • Hi,

    As already replied via E-Mail:
    Currently, ETB is officialy implemented and tested for Cortex A8 but not for Cortex A9.
    It may be possible that there are small changes between Cortex A8 and Cortex A9 regarding ETB.
    We have to check this.

    Keep you posted.


    Best regards
    Erik
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi,

    It's the other way around:
    It has been implemented and tested on Cortex-A9 (Renesas RZ device) but not for A8 so far.
    I assume that the protocol / output is pretty similar, but you never know. Needs to be checked.


    Best regards
    Alex
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.