Hi All,
I recently purchased J-Link EDU. I am trying to debug secondary core of Xilinx Zynq processor on my zedboard(Zynq 7020). I followed the procedure mentioned in the following link

Debugging second core in OMAP4430


I created J-Link script with the reference mentioned in the link(debug address base changed to suit zynq secondary processor)

void InitTarget(void) {
Report("Connect to 2nd A9 core");
JTAG_DRPre = 1;
JTAG_DRPost = 0;
JTAG_IRPre = 6;
JTAG_IRPost = 0;
JTAG_IRLen = 4;
CPU = CORTEX_A9;
// JTAG_AllowTAPReset = 1;
//
// Base address of debug registers differs from device to device, so this needs to be adapted
//
//CORESIGHT_CoreBaseAddr = 0x80090000; // Base address of debug registers of first core
CORESIGHT_CoreBaseAddr = 0x80092000; // Base address of debug registers of second core.
}

Even with this, J-Link is always connected to Core0.

Has anybody succeeded in doing this? Can you please post some pointers in order to debug secondary core

J-Link Details:
hardware: J-Link EDU V9.0
Jlink software version: latest available on Linux host.