from IAR workbench, seems to start up and communicate but then get a dialog:
larldePm - Execution failure in flash loader
Any ideas? Log below
Tue Aug 26, 2014 10:05:17: Loaded macro file: D:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\debugger\ST\STM32F4xx.dmac
Tue Aug 26, 2014 10:05:17: Loaded macro file: D:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\ST\FlashSTM32F4xxx.mac
Tue Aug 26, 2014 10:05:24: Updating firmware: J-Link ARM V8 compiled Jul 17 2014 12:31:18
Tue Aug 26, 2014 10:05:24: Replacing firmware: J-Link ARM V8 compiled Nov 25 2013 19:20:08
Tue Aug 26, 2014 10:05:28: Waiting for new firmware to boot
Tue Aug 26, 2014 10:05:30: New firmware booted successfully
Tue Aug 26, 2014 10:05:30: JLINK command: ProjectFile = C:\work\firmware\trunk\STM\Project\avi\printer\iar\settings\usbd_vcp_STM324xG-EVAL_USBD-FS.jlink, return = 0
Tue Aug 26, 2014 10:05:30: Device "STM32F405ZG" selected (1024 KB flash, 128 KB RAM).
Tue Aug 26, 2014 10:05:30: DLL version: V4.90b, compiled Aug 14 2014 09:40:57
Tue Aug 26, 2014 10:05:30: Firmware: J-Link ARM V8 compiled Jul 17 2014 12:31:18
Tue Aug 26, 2014 10:05:30: Selecting SWD as current target interface.
Tue Aug 26, 2014 10:05:30: JTAG speed is initially set to: 32 kHz
Tue Aug 26, 2014 10:05:30: Found SWD-DP with ID 0x2BA01477
Tue Aug 26, 2014 10:05:31: Found SWD-DP with ID 0x2BA01477
Tue Aug 26, 2014 10:05:31: Found Cortex-M4 r0p1, Little endian.
Tue Aug 26, 2014 10:05:31: FPUnit: 6 code (BP) slots and 2 literal slots
Tue Aug 26, 2014 10:05:31: TPIU fitted.
Tue Aug 26, 2014 10:05:31: ETM fitted.
Tue Aug 26, 2014 10:05:31: Hardware reset with strategy 0 was performed
Tue Aug 26, 2014 10:05:31: Initial reset was performed
Tue Aug 26, 2014 10:05:31: Setting FLASH readout protection level 0 (disabled)
Tue Aug 26, 2014 10:05:41: Hardware reset with strategy 2 was performed
Tue Aug 26, 2014 10:05:41: 1248 bytes downloaded and verified (6.00 Kbytes/sec)
Tue Aug 26, 2014 10:05:41: Loaded debugee: D:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\ST\FlashSTM32F4xxx.out
Tue Aug 26, 2014 10:05:41: Target reset
Tue Aug 26, 2014 10:05:43: Unloaded macro file: D:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\ST\FlashSTM32F4xxx.mac
Tue Aug 26, 2014 10:05:43: Execution failure in flash loader.
larldePm - Execution failure in flash loader
Any ideas? Log below
Tue Aug 26, 2014 10:05:17: Loaded macro file: D:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\debugger\ST\STM32F4xx.dmac
Tue Aug 26, 2014 10:05:17: Loaded macro file: D:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\ST\FlashSTM32F4xxx.mac
Tue Aug 26, 2014 10:05:24: Updating firmware: J-Link ARM V8 compiled Jul 17 2014 12:31:18
Tue Aug 26, 2014 10:05:24: Replacing firmware: J-Link ARM V8 compiled Nov 25 2013 19:20:08
Tue Aug 26, 2014 10:05:28: Waiting for new firmware to boot
Tue Aug 26, 2014 10:05:30: New firmware booted successfully
Tue Aug 26, 2014 10:05:30: JLINK command: ProjectFile = C:\work\firmware\trunk\STM\Project\avi\printer\iar\settings\usbd_vcp_STM324xG-EVAL_USBD-FS.jlink, return = 0
Tue Aug 26, 2014 10:05:30: Device "STM32F405ZG" selected (1024 KB flash, 128 KB RAM).
Tue Aug 26, 2014 10:05:30: DLL version: V4.90b, compiled Aug 14 2014 09:40:57
Tue Aug 26, 2014 10:05:30: Firmware: J-Link ARM V8 compiled Jul 17 2014 12:31:18
Tue Aug 26, 2014 10:05:30: Selecting SWD as current target interface.
Tue Aug 26, 2014 10:05:30: JTAG speed is initially set to: 32 kHz
Tue Aug 26, 2014 10:05:30: Found SWD-DP with ID 0x2BA01477
Tue Aug 26, 2014 10:05:31: Found SWD-DP with ID 0x2BA01477
Tue Aug 26, 2014 10:05:31: Found Cortex-M4 r0p1, Little endian.
Tue Aug 26, 2014 10:05:31: FPUnit: 6 code (BP) slots and 2 literal slots
Tue Aug 26, 2014 10:05:31: TPIU fitted.
Tue Aug 26, 2014 10:05:31: ETM fitted.
Tue Aug 26, 2014 10:05:31: Hardware reset with strategy 0 was performed
Tue Aug 26, 2014 10:05:31: Initial reset was performed
Tue Aug 26, 2014 10:05:31: Setting FLASH readout protection level 0 (disabled)
Tue Aug 26, 2014 10:05:41: Hardware reset with strategy 2 was performed
Tue Aug 26, 2014 10:05:41: 1248 bytes downloaded and verified (6.00 Kbytes/sec)
Tue Aug 26, 2014 10:05:41: Loaded debugee: D:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\ST\FlashSTM32F4xxx.out
Tue Aug 26, 2014 10:05:41: Target reset
Tue Aug 26, 2014 10:05:43: Unloaded macro file: D:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\ST\FlashSTM32F4xxx.mac
Tue Aug 26, 2014 10:05:43: Execution failure in flash loader.