Hi,

I flashed some code that configures the core clock incorrectly to 20 MHz instead of 80 MHz. At some point I found that I could no longer download and debug code with IAR. I keep getting the errors below. I'm not sure if the 20 MHz has anything to do with it but I thought I'd mention it because the same firmware running on a previous version of the silicon still connects/debugs/runs just fine at 80. I have another chip of the new silicon and it behaves the same way.

From J-Link Commander I can halt, single-step, and go although you can see that it fails at first and then connects at slower speed.

I tried JFlash for the heck of it. Using the project for this device I tried to have it erase the chip but it fails saying that it could not write to RAM (I can connect-only using IAR and write to RAM).

Thanks for reading,

Kenny

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SEGGER J-Link Commander V4.86b ('?' for help)
Compiled Jun 27 2014 20:11:09
DLL version V4.86b, compiled Jun 27 2014 20:11:00
Firmware: J-Link V9 compiled May 23 2014 19:21:14
Hardware: V9.00
S/N: 609300309
Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTarget = 3.250V
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
No devices found on JTAG chain. Trying to find device on SWD.
Info: Found SWD-DP with ID 0x2BA01477
Info: Found SWD-DP with ID 0x2BA01477
No device found on SWD.
Trying to find device on FINE interface.
No device found on FINE interface.
Did not find any core.
Failed to identify target. Trying again with slow (4 kHz) speed.
No devices found on JTAG chain. Trying to find device on SWD.
Info: Found SWD-DP with ID 0x2BA01477
Info: Found Cortex-M3 r2p1, Little endian.
Info: FPUnit: 2 code (BP) slots and 0 literal slots
Cortex-M3 identified.
-------------------------------------------------------------------------

IAR Output


Mon Jun 30, 2014 18:07:00: Device "ADUCM320" selected (256 KB flash, 32 KB RAM).
Mon Jun 30, 2014 18:07:00: DLL version: V4.86b, compiled Jun 27 2014 20:11:00
Mon Jun 30, 2014 18:07:00: Firmware: J-Link V9 compiled May 23 2014 19:21:14
Mon Jun 30, 2014 18:07:00: Selecting SWD as current target interface.
Mon Jun 30, 2014 18:07:00: JTAG speed is fixed to: 6000 kHz
Mon Jun 30, 2014 18:07:00: Found SWD-DP with ID 0x2BA01477
Mon Jun 30, 2014 18:07:00: Found Cortex-M3 r2p1, Little endian.
Mon Jun 30, 2014 18:07:00: FPUnit: 2 code (BP) slots and 0 literal slots
Mon Jun 30, 2014 18:07:01: Core did not halt after reset, manually halting CPU...
Mon Jun 30, 2014 18:07:01: Warning: CPU could not be halted
Mon Jun 30, 2014 18:07:01: Warning: CPU did not halt after reset.
Mon Jun 30, 2014 18:07:01: Hardware reset with strategy 0 was performed
Mon Jun 30, 2014 18:07:01: Initial reset was performed
Mon Jun 30, 2014 18:07:01: Warning: CPU could not be halted
Mon Jun 30, 2014 18:07:05: Fatal error: Failed to read CPUID for Cortex device Session aborted!
Mon Jun 30, 2014 18:07:05: Failed to load flash loader: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\AnalogDevices\FlashADuCM320.flash

For posterity:

This issue was caused by configuring the GPIO pin that also determines the boot mode as an output (P2.3/BM). The released silicon retains the configuration of I/O through a software reset by default and it caused the bootloader to be invoked. The previous silicon did not have this feature.

Another bit that is somewhat confusing for this ADI part is that you must use reset strategy 7 "Halt after Kernel". In IAR it is called "Halt after Bootloader", which is the name of another reset strategy. In IARs log you can see that reset strategy 7 is indeed being used.

Can't seem to get the code formatting to work correctly. I've edited the snippet below several times and in preview it puts it back. Had this happen before. Seems to happen pasting from VMWare Fusion into Chrome running on the Apple side. This is getting meta.