Dear All,
In our setup, we have the A9 Dual core IP programmed on an FPGA (it's not a real chip but other than working slower, it should be exactly the same).
We managed to execute code which uses both code so we know that they are both functional however JLink recognizes only on core.
I'm adding the JLink log at the end of this correspondence.
Do you have a suggestion?
Many Thanks!
Hila
C:\Program Files\SEGGER\JLinkARM_V480g>JLink.exe
SEGGER J-Link Commander V4.80g ('?' for help)
Compiled Feb 13 2014 20:50:11
DLL version V4.80g, compiled Feb 13 2014 20:50:02
Firmware: J-Link V9 compiled Jan 10 2014 19:51:25
Hardware: V9.00
S/N: 59104821
Feature(s): GDB
VTarget = 3.293V
Info: TotalIRLen = 4, IRPrint = 0x01
Info: ARM AP[0]: 0x44770001, AHB-AP
Info: ARM AP[1]: 0x24770002, APB-AP
Info: Found Cortex-A9 r4p1
Info: 6 code breakpoints, 4 data breakpoints
Info: Data endian: little
Info: Main ID register: 0x414FC091
Info: L1 (I-cache): 32 KB, 256 sets, LineSize 32 bytes, 4-way
Info: L1 (D-cache): 32 KB, 256 sets, LineSize 32 bytes, 4-way
Info: System control register:
Info: Instruction endian: little
Info: Level-1 instruction cache enabled
Info: Level-1 data cache disabled
Info: MMU disabled
Info: Branch prediction enabled
Found 1 JTAG device, Total IRLen = 4:
#0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight
JTAG-DP (ARM)
Cortex-A9 identified.
Target interface speed: 100 kHz
J-Link>
In our setup, we have the A9 Dual core IP programmed on an FPGA (it's not a real chip but other than working slower, it should be exactly the same).
We managed to execute code which uses both code so we know that they are both functional however JLink recognizes only on core.
I'm adding the JLink log at the end of this correspondence.
Do you have a suggestion?
Many Thanks!
Hila
C:\Program Files\SEGGER\JLinkARM_V480g>JLink.exe
SEGGER J-Link Commander V4.80g ('?' for help)
Compiled Feb 13 2014 20:50:11
DLL version V4.80g, compiled Feb 13 2014 20:50:02
Firmware: J-Link V9 compiled Jan 10 2014 19:51:25
Hardware: V9.00
S/N: 59104821
Feature(s): GDB
VTarget = 3.293V
Info: TotalIRLen = 4, IRPrint = 0x01
Info: ARM AP[0]: 0x44770001, AHB-AP
Info: ARM AP[1]: 0x24770002, APB-AP
Info: Found Cortex-A9 r4p1
Info: 6 code breakpoints, 4 data breakpoints
Info: Data endian: little
Info: Main ID register: 0x414FC091
Info: L1 (I-cache): 32 KB, 256 sets, LineSize 32 bytes, 4-way
Info: L1 (D-cache): 32 KB, 256 sets, LineSize 32 bytes, 4-way
Info: System control register:
Info: Instruction endian: little
Info: Level-1 instruction cache enabled
Info: Level-1 data cache disabled
Info: MMU disabled
Info: Branch prediction enabled
Found 1 JTAG device, Total IRLen = 4:
#0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight
JTAG-DP (ARM)
Cortex-A9 identified.
Target interface speed: 100 kHz
J-Link>