Setup:
IDE = IAR 6.30.6.3387
JLink = JLink ARM v8 (SWD with no SWO)
Device = STM32F051x8
JLink DLL Version = 44201
According to my project settings the SWO Clock is set to 2000kHz, however in the cspy log I see the following:
T143C 004:705 JLINK_GetSpeed() returns 0x20 (0000ms, 4656ms total)
T143C 004:705 JLINK_SetMaxSpeed() (0001ms, 4656ms total)
Problem:
I have two development boards (Rev1 and Rev2).
Rev 2 has some layout changes but no functional or part value changes (especially in the SWD area)
I am using the exact same code/project on both boards.
On Rev 1, I have no problems what so ever with debugging.
On Rev 2, I get 'Failed to get CPU status after 4 retries' very often when debugging. Not every time, but at least 7 of 10 times once I hit the download and debug button.
Investigation:
When I look at the cspy outputs I notice that the return code to JLINK_IsHalted Command is ERROR on the Rev 2 board when I get the error dialog from IAR. On the Rev 1 board I only ever get FALSE/TRUE return codes.
T1C68 023:679 JLINK_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC ) returns 0x04 (0001ms, 6171ms total)
T1C68 023:680 JLINK_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028 ) returns 0x04 (0001ms, 6172ms total)
T1C68 023:681 JLINK_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038 ) returns 0x04 (0001ms, 6173ms total)
T1C68 023:682 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008 ) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014 ) (0006ms, 6174ms total)
T1C68 023:689 JLINK_IsHalted() returns FALSE (0000ms, 6180ms total)
T1C68 023:691 JLINK_IsHalted() returns ERROR (0000ms, 6180ms total)
T1C68 023:691 JLINK_IsHalted() returns ERROR (0001ms, 6180ms total)
Questions:
1) What exactly is the JLINK_IsHalted command considering an "ERROR"?
2) Is there a way to script out the IAR debug sequence exactly so that I can attempt to replicate the failure outside of IAR. That way I have a mechanism to reproduce the problem for the hardware guy. (Also, so I can confirm the failure is fixed when a "fix" is found). I have tried using the JLink Command line tool, but I don't see an explict IsHalted Command. Note: I tried running the 1000 HaltGo test and did not have any issues on both boards.
3) Any suggestions about signal integrity on the SWD signal lines? Possibly what irregulaties I should be looking for if I probe the lines.
4) I don't see how the actual software running on the micro can be affecting the debugger, is this a good/accurate assumption?
5) Any other suggestions on how to more efficetly reproduce the problem and/or suggestions on how to fix the issue.
IDE = IAR 6.30.6.3387
JLink = JLink ARM v8 (SWD with no SWO)
Device = STM32F051x8
JLink DLL Version = 44201
According to my project settings the SWO Clock is set to 2000kHz, however in the cspy log I see the following:
T143C 004:705 JLINK_GetSpeed() returns 0x20 (0000ms, 4656ms total)
T143C 004:705 JLINK_SetMaxSpeed() (0001ms, 4656ms total)
Problem:
I have two development boards (Rev1 and Rev2).
Rev 2 has some layout changes but no functional or part value changes (especially in the SWD area)
I am using the exact same code/project on both boards.
On Rev 1, I have no problems what so ever with debugging.
On Rev 2, I get 'Failed to get CPU status after 4 retries' very often when debugging. Not every time, but at least 7 of 10 times once I hit the download and debug button.
Investigation:
When I look at the cspy outputs I notice that the return code to JLINK_IsHalted Command is ERROR on the Rev 2 board when I get the error dialog from IAR. On the Rev 1 board I only ever get FALSE/TRUE return codes.
T1C68 023:679 JLINK_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC ) returns 0x04 (0001ms, 6171ms total)
T1C68 023:680 JLINK_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028 ) returns 0x04 (0001ms, 6172ms total)
T1C68 023:681 JLINK_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038 ) returns 0x04 (0001ms, 6173ms total)
T1C68 023:682 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008 ) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014 ) (0006ms, 6174ms total)
T1C68 023:689 JLINK_IsHalted() returns FALSE (0000ms, 6180ms total)
T1C68 023:691 JLINK_IsHalted() returns ERROR (0000ms, 6180ms total)
T1C68 023:691 JLINK_IsHalted() returns ERROR (0001ms, 6180ms total)
Questions:
1) What exactly is the JLINK_IsHalted command considering an "ERROR"?
2) Is there a way to script out the IAR debug sequence exactly so that I can attempt to replicate the failure outside of IAR. That way I have a mechanism to reproduce the problem for the hardware guy. (Also, so I can confirm the failure is fixed when a "fix" is found). I have tried using the JLink Command line tool, but I don't see an explict IsHalted Command. Note: I tried running the 1000 HaltGo test and did not have any issues on both boards.
3) Any suggestions about signal integrity on the SWD signal lines? Possibly what irregulaties I should be looking for if I probe the lines.
4) I don't see how the actual software running on the micro can be affecting the debugger, is this a good/accurate assumption?
5) Any other suggestions on how to more efficetly reproduce the problem and/or suggestions on how to fix the issue.