Hardware reset strategies when using SWD to debug Cortex-M3

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  • Hardware reset strategies when using SWD to debug Cortex-M3

    I read the J-Link manual for different hardware reset strategies. However, it seems only dedicated to JTAG interface (e.g. nRESET and nTRST are coupled or not ...). Does anybody know the situation when using SWD interface to debug Cortex-M3? E.g. how to ensure the ARM core to be halted before executing any instruction, thank you.

    The post was edited 2 times, last by redstring ().

  • Hello redstring,

    When using SWD interface, the same reset strategies as when
    using JTAG interface with Cortex-M3, are available.

    These reset strategies are:
    NORMAL (Using RESET pin, halting CPU after Reset.)
    CORE (Resets the core only, not peripherals.)
    RESETPIN (Resets core & peripherals using RESET pin.)

    We will add them to the J-Link / J-Trace manual.

    Best regards,

    Alex
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