Hello, I had been debugging for several weeks with the J-Link interface, but yesterday I started having problems. J-Link can no longer halt my CPU. I replaced the K53 on my board with a new chip, but am still having the exact same result. What could be wrong? Thanks!
J-Link Commander shows the following output:
SEGGER J-Link Commander V4.42a ('?' for help)
Compiled Feb 8 2012 19:01:28
DLL version V4.42a, compiled Feb 8 2012 19:01:12
Firmware: J-Link Lite-FSL V1 compiled Jan 31 2011 11:00:51
Hardware: V1.00
S/N: 430110131
VTarget = 3.437V
Info: TotalIRLen = 4, IRPrint = 0x01
Info: Found Cortex-M4 r0p0, Little endian.
Info: TPIU fitted.
Info: ETM fitted.
Info: ETB present.
Info: CSTF present.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Found 1 JTAG device, Total IRLen = 4:
#0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
JTAG speed: 100 kHz
J-Link>si 1
Selecting SWD as current target interface.
Setting target interface speed to 1MHz. Use "Speed" to change.
J-Link>rsettype 6
Info: Found SWD-DP with ID 0x2BA01477
Info: TPIU fitted.
Info: ETM fitted.
Info: ETB present.
Info: CSTF present.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: Found Cortex-M4 r0p0, Little endian.
Reset type KINETIS: Reset via strategy NORMAL. Watchdog will be disabled after r
eset
J-Link>rx 0
Reset delay: 0 ms
Reset type KINETIS: Reset via strategy NORMAL. Watchdog will be disabled after r
eset
Info: Found SWD-DP with ID 0x2BA01477
Info: TPIU fitted.
Info: ETM fitted.
Info: ETB present.
Info: CSTF present.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: Found Cortex-M4 r0p0, Little endian.
WARNING: S_RESET_ST not cleared
WARNING: CPU did not halt after reset.
WARNING: CPU could not be halted
Info: Core did not halt after reset, trying to disable WDT.
WARNING: CPU did not halt after reset.
WARNING: CPU could not be halted
WARNING: S_RESET_ST not cleared
WARNING: T-bit of XPSR is 0 but should be 1. Changed to 1.
WARNING: CPU did not halt after reset.
****** Error: CPU not halted
J-Link Commander shows the following output:
SEGGER J-Link Commander V4.42a ('?' for help)
Compiled Feb 8 2012 19:01:28
DLL version V4.42a, compiled Feb 8 2012 19:01:12
Firmware: J-Link Lite-FSL V1 compiled Jan 31 2011 11:00:51
Hardware: V1.00
S/N: 430110131
VTarget = 3.437V
Info: TotalIRLen = 4, IRPrint = 0x01
Info: Found Cortex-M4 r0p0, Little endian.
Info: TPIU fitted.
Info: ETM fitted.
Info: ETB present.
Info: CSTF present.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Found 1 JTAG device, Total IRLen = 4:
#0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
JTAG speed: 100 kHz
J-Link>si 1
Selecting SWD as current target interface.
Setting target interface speed to 1MHz. Use "Speed" to change.
J-Link>rsettype 6
Info: Found SWD-DP with ID 0x2BA01477
Info: TPIU fitted.
Info: ETM fitted.
Info: ETB present.
Info: CSTF present.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: Found Cortex-M4 r0p0, Little endian.
Reset type KINETIS: Reset via strategy NORMAL. Watchdog will be disabled after r
eset
J-Link>rx 0
Reset delay: 0 ms
Reset type KINETIS: Reset via strategy NORMAL. Watchdog will be disabled after r
eset
Info: Found SWD-DP with ID 0x2BA01477
Info: TPIU fitted.
Info: ETM fitted.
Info: ETB present.
Info: CSTF present.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: Found Cortex-M4 r0p0, Little endian.
WARNING: S_RESET_ST not cleared
WARNING: CPU did not halt after reset.
WARNING: CPU could not be halted
Info: Core did not halt after reset, trying to disable WDT.
WARNING: CPU did not halt after reset.
WARNING: CPU could not be halted
WARNING: S_RESET_ST not cleared
WARNING: T-bit of XPSR is 0 but should be 1. Changed to 1.
WARNING: CPU did not halt after reset.
****** Error: CPU not halted